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Cadence and MIPS Technologies Deliver Encounter Reference Methodology for Industry's Highest Performance 32-Bit Core Family
Using the Industry-Standard Cadence RTL-to-GDSII Flow, Customers
of the 24K(TM) Core Family Have a Path to High Quality of Silicon
SAN JOSE, Calif. & MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—April 5, 2004—
Cadence Design Systems, Inc. (NYSE:CDN) and MIPS Technologies,
Inc. (Nasdaq:MIPS) announced the availability of an optimized
MIPS-Cadence(R) Encounter(TM) Reference Methodology for customers of
MIPS32(R) 24K(TM) cores, which is the embedded industry's highest
performing 32-bit synthesizable core family available for licensing
(see related announcement by MIPS Technologies). Available to
customers of the 24K core family, the optimized Encounter digital IC
design platform delivers superior performance and ease-of-use to
MIPS-Based(TM) system-on-chip (SoC) designers by incorporating the SoC
Encounter RTL-to-GDSII system and Encounter RTL Compiler synthesis
with the support for a generic 130 nanometer process.
At nanometer geometries, SoC performance is dominated by the
timing and noise behavior of a chip's routed wires. The Encounter
Reference Methodology optimized for the 24K core family provides an
integrated, wire-centric RTL-to-GDSII core implementation for
customers, fulfilling the objective to optimize the silicon design
chain by providing better quality of silicon (QoS). The Encounter
platform integrates best-of-breed technology for wire-centric design
with RTL Compiler synthesis, First Encounter(R) for silicon virtual
prototyping, NanoRoute(TM) nanometer router technology for signal
integrity (SI) aware routing, and CeltIC(TM) SI and VoltageStorm(TM)
tools for signal integrity signoff. This Reference Methodology enables
customers to achieve improved QoS, the new metric of silicon quality
measured after wires for accuracy.
"As MIPS Technologies pushes the limits of performance in
synthesizable microprocessor technology, it's important that we ensure
customers have the technologies with which to meet their design goals
quickly," said Victor Peng, vice president, engineering, MIPS
Technologies. "By working closely with Cadence on the 24K reference
flow, we have enabled our customers to produce hardened 24K databases
that achieve high frequencies and small die areas with reduced
runtimes."
"We are pleased with the role of RTL Compiler global synthesis
technology in optimizing the silicon design chain. The results of our
teamwork with MIPS Technologies enable us to provide our mutual
customers with a predictable path from RTL to better first silicon.
This new MIPS-Cadence Encounter Reference Methodology for use with 24K
cores can eliminate weeks from our customers' efforts to implement 24K
core designs," said Dr. Chi-Ping Hsu, corporate vice president,
synthesis solutions, Cadence Design Systems, Inc.
"The Artisan SAGE-HS Libraries are specifically designed for
high-performance consumer electronics," said Neal Carney, vice
president of marketing at Artisan. "We are pleased that Artisan
libraries were chosen to help launch the high-performance core and the
MIPS-Cadence Encounter 24K reference methodology."
In order to achieve high QoS with an industry-standard design
flow, MIPS Technologies is using the Encounter platform's wires-first
methodology and best-of-breed technologies, such as Encounter RTL
Compiler and the SoC Encounter RTL-GDSII system. The SoC Encounter
system offers integrated silicon virtual prototyping, physical
implementation, SI-aware routing and signal integrity technologies for
nanometer designs, like the 24K core design.
About Cadence Encounter RTL Compiler
The Encounter RTL Compiler system replaces traditional design
flows with a new design strategy that minimizes time-to-wires and
full-chip iteration time. Encounter RTL Compiler provides a higher
level of QoS by measuring a design's physical characteristics in terms
of area, performance, and power -- using wires. The technology behind
Encounter RTL Compiler synthesis delivers global optimization for
timing closure using a set of global algorithms that produce
outstanding results at each stage of implementation, including a
better starting point for routing complex, wire-centric designs. The
Encounter RTL Compiler is used throughout the silicon design chain by
application-specific integrated circuit (ASIC) and intellectual
property (IP) vendors, and IC designers to help increase overall chip
speed. It can also help to reduce turnaround time.
About the MIPS32 24K Core Family
The MIPS32 24K core family, which includes the 24Kc(TM), 24Kc Pro,
24Kf(TM) and 24Kf Pro versions, offers performance from 400 to 550 MHz
worst case in a 130 nanometer process, the highest frequency available
in 32-bit synthesizable cores for embedded markets, while minimizing
design time and reducing product costs. Tailored SOC design
methodologies, an Open Core Protocol (OCP) interconnect structure,
standard libraries and on-chip memories from industry-leading
companies help speed time-to-market, an important advantage for a
processor core suited to embedded consumer applications such as
digital and interactive TVs, set-top boxes and DVD players.
Availability of the Optimized Cadence Encounter Reference
Methodology
MIPS Technologies is offering customers of the 24K core family the
Cadence Encounter platform reference methodology with the relevant
synthesis scripts and floorplanning information. Support for the
reference methodology is provided by MIPS Technologies. For more
details, visit the MIPS Technologies Website or contact the company at
650-567-5000 or email at sales@mips.com.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard
processor architectures and cores for digital consumer and business
applications. The company drives the broadest architectural alliance
that is delivering 32- and 64-bit embedded RISC solutions. The company
licenses its intellectual property to semiconductor companies, ASIC
developers, and system OEMs. MIPS Technologies and its licensees offer
the widest range of robust, scalable processors in standard, custom,
semi-custom and application-specific products. The company is based in
Mountain View, Calif., and can be reached at 650-567-5000 or
www.mips.com.
About Cadence
Cadence is the largest supplier of electronic design technologies,
methodology services, and design services. Cadence solutions are used
to accelerate and manage the design of semiconductors, computer
systems, networking and telecommunications equipment, consumer
electronics, and a variety of other electronics-based products. With
approximately 4,800 employees and 2003 revenues of approximately $1.1
billion, Cadence has sales offices, design centers, and research
facilities around the world. The company is headquartered in San Jose,
Calif., and traded on the New York Stock Exchange under the symbol
CDN. More information about the company, its products and services is
available at www.cadence.com.
MIPS and MIPS32 are registered trademarks in the United States and
other countries, and MIPS-Based, 24K, 24Kc and 24Kf are trademarks of
MIPS Technologies, Inc. Cadence and the Cadence logo are registered
trademarks, and CeltIC, Encounter, First Encounter, NanoRoute, and
VoltageStorm are trademarks of Cadence Design Systems, Inc. All other
trademarks are the property of their respective owners.
Contact:
MIPS Technologies, Inc.
Lee Garvin Flanagin, 650-567-5180
flanagin@mips.com
or
The Hoffman Agency for Cadence Design Systems
Carolyn Robinson, 408-975-3065
crobinson@hoffman.com
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